Launched a special hiring program for M.Tech Final year/2019 passed out in ASIC Design Verification

Excel VLSI and Entuple come together to build a strong ASIC DV team hiring good M.Tech candidates.
They shall be trained for 9-12 Months in Design Verification concepts, various protocols used, SoC Verification and test bench Automation and deployed to internal projects.
M.Tech candidates can also get assistance on their final year project and execute as part of their training program.
Interested candidates can contact us for more information and register in link :